Contacts for semiconductor devices

ABSTRACT

In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.

RELATED APPLICATIONS

The present application is a continuation of U.S. Non-Provisional application No. 16/701,496, filed on Dec. 3, 2019, which claims priority to U.S. Non-Provisional application No. 14/059,077, filed on Oct. 21, 2013, now U.S. Pat. No. 10,516,044, issued on Dec. 24, 2019, which claims priority to U.S. Non-Provisional application No. 11/551,532, filed on Oct. 20, 2006, now U.S. Pat. No. 8,564,041, issued on Oct. 22, 2013, all of which are incorporated by reference herein in their entirety.

TECHNICAL FIELD

The invention related generally to semiconductor devices and methods of manufacturing semiconductor devices. The invention has particular applicability to memory devices and the formation of contacts for memory devices.

BACKGROUND ART

The escalating demands for high density and performance associated with non-volatile memory devices, such as electrically erasable programmable read only memory (EEPROM) devices, require small design features, high reliability and increased manufacturing throughput. The reduction of design features, however, challenges the limitations of conventional methodology.

One particular problem with non-volatile memory devices involves charge leakage from contacts. For example, as device dimensions become smaller and chip sizes decrease, charge leakage from a contact to the charge storage element of a memory cell may occur. The charge leakage may occur when electrons travel laterally from the contact through a dielectric layer into the charge storage element or vice versa. Charge leakage currents may make it difficult for the memory device to be efficiently programmed or erased. In addition, the charge leakage may also make it difficult for the memory device to meet the expected data retention requirements and, ultimately, may lead to device failure.

DISCLOSURE OF THE INVENTION

Advantages and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages and features of the invention may be realized and obtained as particularly pointed out in the appended claims.

According to one aspect consistent with the invention, a memory device is provided. The memory device includes a substrate, a first dielectric layer formed over the substrate, a charge storage element formed over the first dielectric layer, a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer. The memory device also includes an interlayer dielectric layer formed over the control gate, a source region formed in the substrate and a drain region formed in the substrate. The memory device further includes a contact formed in a portion of the interlayer dielectric, the contact having a width ranging from about 400 angstroms (Å) to about 900 Å.

According to another aspect consistent with the invention, a non-volatile memory device that includes a plurality of memory cells is provided. Each of the memory cells includes a first dielectric layer formed on a substrate, a charge storage element formed on the first dielectric layer, an inter-gate dielectric formed on the charge storage element, a control gate formed over the inter-gate dielectric, a source region formed in the substrate and a drain region formed in the substrate. The non-volatile memory device also includes a second dielectric layer formed over the plurality of memory cell and a contact formed in a portion of the second dielectric layer. The contact has a width of less than 1200 Å.

According to a further aspect consistent with the invention, a memory device is provided. The memory device includes a plurality of memory cells and a dielectric layer formed over the plurality of memory cells. The memory device also includes a plurality of contacts formed in the dielectric layer. Each of the plurality of contacts has a width of less than 1400 Åand is formed adjacent at least one of a source region or a drain region of one of the plurality of memory cells.

Other advantages and features of the invention will become readily apparent to those skilled in this art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings are to be regarded as illustrative in nature, and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

Reference is made to the attached drawings, wherein elements having the same reference number designation may represent like elements throughout.

FIG. 1 is a cross-section illustrating exemplary layers used to form memory cells in an exemplary embodiment of the invention.

FIG. 2 is a cross-section illustrating the formation of exemplary memory cells in accordance with an exemplary embodiment of the invention.

FIG. 3 is a cross-section illustrating the formation of spacers adjacent the side surfaces of the memory cells of FIG. 2.

FIGS. 4A and 4B are cross-sections illustrating the formation of an interlayer dielectric on the device of FIG. 3.

FIGS. 5A-5C are cross-sections illustrating the formation of an exemplary contact in the interlayer dielectric of FIG. 4.

FIG. 6 is a cross-section illustrating the formation of conductive layer on the device of FIG. 5C.

FIG. 7 is a cross-section illustrating the formation of an interlayer dielectric on the device of FIG. 6.

FIG. 8 is a cross-section illustrating the formation of a via in the interlayer dielectric of FIG. 7.

FIG. 9 is a cross-section illustrating the formation of a conductive layer on the device of FIG. 8.

FIG. 10 is a cross-section illustrating the formation of a dielectric layer on the device of FIG. 9.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 illustrates the cross-section of a semiconductor device 100 formed in accordance with an embodiment of the invention. Referring to FIG. 1, semiconductor device 100 may include layers 110, 120, 130, 140 and 150. In an exemplary embodiment, layer 110 may be a substrate of semiconductor device 100 and may include silicon, germanium, silicon-germanium or other semiconducting materials. In alternative implementations, layer 110 may be a conductive layer or a dielectric layer formed a number of layers above the surface of a substrate in semiconductor device 100.

Layer 120 may be a dielectric layer formed on layer 110 in a conventional manner. In an exemplary implementation, dielectric layer 120 may include an oxide, such as a silicon oxide (e.g., SiO₂), and may have a thickness ranging from, for example, about 30 angstroms (Å) to about 100 Å. Dielectric layer 120 may function as a tunnel oxide layer for a subsequently formed memory cell of semiconductor device 100.

Layer 130 may be formed on layer 120 in a conventional manner and may include a dielectric material, such as a nitride (e.g., a silicon nitride) or an oxynitride. Layer 130, consistent with the invention, may act as a charge storage layer for semiconductor device 100 and may have a thickness ranging from, for example, about 40 Å to about 100 Å. In alternative implementations, layer 130 may include a conductive material, such as polycrystalline silicon, used to form a floating gate electrode. In this implementation, layer 130 may have a thickness ranging from about 500 Å to about 1,000 Å.

Layer 140 may be formed on layer 130 in a conventional manner and may include a dielectric material, such as an oxide (e.g., SiO₂). Alternatively, layer 140 may include another material having a high dielectric constant (K), such as aluminum oxide or hafnium oxide, that may be deposited or thermally grown on layer 130. In still other alternatives, layer 140 may be a composite that includes a number of dielectric layers or films. Layer 140 may have a thickness ranging from, for example, about 40 Å to about 100 Å and may function as an inter-gate dielectric for memory cells in semiconductor device 100.

Layer 150 may include a conductive material, such as polycrystalline silicon, formed on layer 140 in a conventional manner. Alternatively, layer 150 may include other semiconducting materials, such as germanium or silicon-germanium, or various metals, such as titanium or tungsten. Layer 150, consistent with the invention, may be used to form one or more control gate electrodes for one or more memory cells in semiconductor device 100. In an exemplary implementation, layer 150 may have a thickness ranging from, for example, about 1,000 Å to about 2,000 Å.

A photoresist material may be patterned and etched to form masks 160 on the top surface of layer 150, as illustrated in FIG. 1. Masks 160 may be used to facilitate formation of one or more memory cells in semiconductor device 100, as described in more detail below.

Semiconductor device 100 may then be etched, as illustrated in FIG. 2. Referring to FIG. 2, layers 120-150 may be etched in a conventional manner with the etching terminating at substrate 110, thereby forming structures 210. Alternatively, the etching may terminate at an other layer, such as layer 140, followed in some implementations by additional etching, to form structures 210. Each structure 210 (also referred to herein as a memory cell 210) may represent a memory cell of semiconductor device 100, where each memory cell 210 includes a dielectric layer 120, a charge storage layer 130, an inter-gate dielectric layer 140 and a control gate electrode 150. Only two memory cells 210 are illustrated in semiconductor device 100 in FIG. 2 for simplicity. It should be understood that semiconductor device 100 may typically include a memory array including a large number of memory cells 210.

In an exemplary implementation consistent with the invention, each memory cell 210 may be a SONOS-type memory cell, with a silicon control gate electrode 150 formed on an oxide-nitride-oxide (ONO) stack (i.e., layers 140, 130 and 120), with nitride layer 130 acting as a charge storage layer, and the ONO stack being formed on a silicon substrate 110. In alternative implementations, each memory cell 210 may be a floating gate memory cell, with a silicon control gate electrode 150, an inter-gate dielectric 140, a polysilicon floating gate electrode 130 and a tunnel oxide layer 120 formed on substrate 110.

Source and drain regions 220 and 230 may then be formed in substrate 110, as illustrated in FIG. 2. For example, n-type or p-type impurities may be implanted in substrate 110 to form source and drain regions 220 and 230, based on the particular end device requirements. In one implementation, an n-type dopant, such as phosphorous or arsenic, may be implanted. Alternatively, a p-type dopant, such as boron, may be implanted. The particular implantation dosages and energy used to form source and drain regions 220 and 230 may be selected based on the particular end device requirements. One of ordinary skill in the art would be able to optimize the source/drain implantation process based on the particular circuit requirements. It should also be understood that source region 220 and drain region 230 may alternatively be formed at other points in the fabrication process of semiconductor device 100. For example, sidewall spacers may be formed prior to the source/drain ion implantation to control the location of the source/drain junctions based on the particular circuit requirements.

Photoresist masks 160 may be removed using a conventional process. Spacers 310 may be formed adjacent the sidewalls of the memory cells 210, as illustrated in FIG. 3. For example, a dielectric material, such as a silicon oxide, a silicon nitride, a silicon oxynitride or another dielectric material, may be deposited and etched to form spacers 310 on each side of memory cells 210, as illustrated in FIG. 3. Spacers 310 may be used to electrically isolate adjacent memory cells 210 from each other. Spacers 310 may also be used to facilitate the deposition of impurities in semiconductor device 100.

A metal may optionally be deposited over semiconductor device 100, followed by an annealing to form a metal-silicide compound. For example, a metal, such as cobalt, titanium or nickel, may be deposited over the surface of semiconductor device 100. An annealing procedure may be performed to form a metal-silicide layer (not shown) over the surface of control gate electrodes 150. The metal-silicide may also be formed over the portion of source/drain regions 220 and 230 not covered by spacers 310. Unreacted metal may be removed from spacers 310.

A dielectric layer 410 may then be deposited over semiconductor device 100, as illustrated in FIG. 4A. Dielectric layer 410, also referred to as interlayer dielectric (ILD) 410, may include, for example, an oxide (e.g., SiO₂), a boro-phosphosilicate glass (BPSG) material or a phosphosilicate glass (PSG) material. Dielectric layer 410 may have a thickness ranging from about 6,000 Å to about 10,000 Å.

ILD 410 may optionally be planarized using a conventional process, such as a chemical-mechanical polishing (CMP) process, as illustrated in FIG. 4B. Referring to FIG. 4B, the CMP process may planarize the top surface of ILD 410 to facilitate formation of subsequent structures, such as interconnect lines. ILD 410, consistent with the invention, may represent an ILD located closest to substrate 110. In alternative implementations, ILD 410 may represent an interlayer dielectric formed a number of layers above the surface of substrate 110. In each case, ILD 410 functions to isolate various conductive structures, such as various interconnect lines described below or to isolate source region 220 or drain region 230 from other conductive structures.

A trench 510, also referred to as contact hole 510, may be formed in ILD 410 using conventional photolithographic and etching techniques, as illustrated in FIG. 5A. Contact hole 510 may be used to form a contact to a source region 220 and/or a drain region 230 of memory cells 210. In an exemplary implementation, the width of contact hole 510 may range from about 0.1 micrometers (μm) to about 0.3 μm.

A dielectric material, such as, for example, a silicon nitride, a silicon oxynitride, or another nitride-based dielectric material, may then be deposited and etched to form spacers 520 on the side surfaces of contact hole 510, as illustrated in FIG. 5B. Alternatively, other dielectric materials, such as a silicon oxide, may be used to form spacers 520. In an exemplary implementation, the width of each of spacers 520 may range from about 50 Å to about 400 Å. In addition, in an exemplary implementation, the height of spacers 520 may range from about 4,000 Å to about 8,000 Å.

Next, a metal layer, such as, for example, tungsten, copper or aluminum, may be deposited to fill contact hole 510 to form contact 530, as illustrated in FIG. 5C. Contact 530 may represent a contact to, for example, the drain region 230 of one memory cell 210 (e.g., the memory cell 210 located on the left side of FIG. 5C) and to the source region 220 of an adjacent memory cell 210 (e.g., the memory cell 210 located on the right side of FIG. 5C). The drain region 230 of the left memory cell 210 in FIG. 5C and the source region 220 of the adjacent memory cell 210 in FIG. 5C may be coupled together to form a bit line. The bit line may be coupled to a column of memory cells 210 (not shown) in a memory cell array. Contact 530 may be used to apply programming and/or erasing voltages to the bit line associated with a column of memory cells 210 based on the particular circuit requirements. Although only one contact 530 is illustrated in FIG. 5C, it should be understood that memory device 100 may include a large number of contacts 530 that may be used to apply voltages to bit lines and/or word lines in memory device 100.

In an exemplary implementation, the width of contact 530 at the lower portion of contact 530, illustrated as W in FIG. 5C, may range from about 900 Å to about 2,200 Å. In another exemplary implementation, the width of contact 530 (i.e., width W in FIG. 5C) may be less than 900 Å. For example, the width W of contact 530 may range from about 400 Å to about 900 Å. In each case, spacers 520 allow narrow contacts (e.g., contact 530) to be formed, while also preventing charge leakage from contact 530 to memory cells 210 and vice versa. For example, spacers 520 provide a dielectric barrier that inhibits contact leakage from contact 530 to charge storage layer 130 and/or to control gate electrode 150 of memory cells 210 and vice versa. Spacers 520 also help improve data retention of memory cells 210 by inhibiting charge gain and/or charge loss caused by electrons traveling from contact 530 into charge storage layer 130 and vice versa. This enables memory cells 210 to be efficiently programmed and/or erased without adverse effects associated with contact leakage currents. In addition, the use of spacers 520 allow contacts 530 to be formed in closer proximity to memory cells 210 than in conventional memory devices, thereby reducing space requirements associated with forming a large array of memory cells.

Excess portions of the metal used to form contact 530 that may be formed over portions of dielectric layer 410 may be removed in some implementations by a planarization process, such as a CMP process. A conductive interconnect line 610 may then be formed over the planarized top surface of ILD 410 and contact 530, as illustrated in FIG. 6. For example, a metal, such as tungsten, copper or aluminum, may be deposited to form conductive line 610 that connects various features in semiconductor device 100, such as source region 220 and/or drain region 230 through contact 530 to an external electrode (not shown). Alternatively, conductive line 610 may connect various memory cells 210 in semiconductor device 100. Conductive line 610 may facilitate programming or erasing various memory cells 210 in semiconductor device 100.

An ILD 710 may be formed over conductive line 610, as illustrated in FIG. 7. ILD 710, consistent with the invention, may include, for example, an oxide, a PSG, a BPSG material or another dielectric material. ILD 710 may have a thickness ranging from about 2,500 Å to about 3,500 Å.

Various back end of line (BEOL) processing may be performed to complete the fabrication of semiconductor device 100. For example, a trench may be formed in ILD 710 followed by deposition of a metal layer, such as copper, aluminum or tungsten, to form via 810, as illustrated in FIG. 8. Via 810 may represent a connection to an uppermost conductive layer of semiconductor device 100. Alternatively, via 810 may represent a connection to any one of a number of conductive layers in semiconductor device 100.

A conductive layer may then be formed over ILD 710. For example, a metal, such as copper or aluminum, may be deposited to form conductive line 910, as illustrated in FIG. 9. Conductive line 910 may represent a BEOL structure or connector that connects various features in semiconductor device 100, such as source and/or drain regions 220/230 to an external electrode (not shown), to facilitate programming or erasing of various memory cells 210 in semiconductor device 100.

A top dielectric layer 1010, also referred to as cap layer 1010, may be formed over conductive line 910. In an exemplary embodiment, cap layer 1010 may be deposited to a thickness ranging from about 6,000 Å to about 10,000 Å. Cap layer 1010 may act as a protective layer to prevent damage to conductive line 910 and other portions of semiconductor device 100 during subsequent processing. For example, cap layer 1010 may protect semiconductor device 100 against impurity contamination during subsequent cleaning processes that may be used to complete a working memory device.

While only two ILDs (i.e., ILDs 410 and 710) and two conductive layers (i.e., layers 610 and 910) are illustrated in FIG. 10 for simplicity, it should be understood that semiconductor device 100 may include more ILD layers and conductive layers based on the particular circuit requirements.

As described above, in an exemplary embodiment, semiconductor device 100 illustrated in FIG. 10 may be a SONOS type memory device, with nitride layer 130 acting as a charge storage element for each memory cell 210. Each memory cell 210 may be an EEPROM type memory device and one or more programming circuits (not shown) may be used to facilitate programming and erasing of one or more memory cells 210 of semiconductor device 100. Programming of each memory cell 210 may be accomplished by applying a voltage to its control gate 150. Once programmed, electrons remain trapped in nitride layer 130 until an erase procedure is performed.

In an exemplary implementation consistent with the invention, each of memory cells 210 illustrated in FIG. 10 may be configured to store two or more bits of data. For example, charge storage layer 130 for each memory cell 210 may be programmed to store charges representing two separate bits of data by localizing the first and second charges to the respective left and right sides of charge storage layer 130 illustrated in FIG. 10. Each of the two bits of memory cell 210 may be programmed independently by, for example, channel hot electron injection, to store charges representing a bit on each respective side of the charge storage layer 130. In this manner, the charges in charge storage layer 130 become effectively trapped on each respective side of charge storage layer 130. Erasing of each bit in memory cell 210 may also be performed independently. During erasing, the charges stored in charge storage layer 130 may tunnel through dielectric layer 120 into the source region 220 and drain region 230, respectively. In alternative implementations, the charge storage layer 130 for each memory cell 210 may be configured to store charges representing three or more bits of data be localizing the charges in charge storage layer 130.

In this manner, the density of the array of memory cells 210 in semiconductor device 100 may be increased as compared to conventional memory devices that store only one bit of data per cell. In alternative implementations, each memory cell 210 may be configured to store a charge representing one bit of data per memory cell 210. In addition, in alternative implementations, semiconductor device 100 may be a floating gate memory device in which layer 130 is formed from a conductive material, such as polysilicon, that functions as a charge storage element for each memory cell 210.

In summary, implementations consistent with the invention form contacts with small device features, thereby reducing space requirements on a chip. Advantageously, the memory cells 210 of semiconductor device 100 exhibit improved resistance to charge leakage and, therefore, increased reliability. In addition, memory cells 210 exhibit improved data retention due to reduced charge gain and/or charge loss problems.

In the previous descriptions, numerous specific details are set forth, such as specific materials, structures, chemicals, processes, etc., in order to provide a thorough understanding of the invention. However, implementations consistent with principles of the invention can be practiced without resorting to the details specifically set forth herein. In other instances, well known processing structures have not been described in detail, in order not to unnecessarily obscure the thrust of the invention.

For example, the dielectric and conductive layers used in manufacturing a semiconductor device in accordance with the invention can be deposited by conventional deposition techniques. For example, various types of chemical vapor deposition (CVD) processes, including low pressure chemical vapor deposition (LPCVD) and enhanced chemical vapor deposition (ECVD) can be employed. In addition, conventional electroplating, photolithographic and etching techniques may also be employed, and hence, the details of such techniques have not been set forth herein in detail.

Implementations of the invention are applicable in the manufacturing of semiconductor devices and particularly in memory devices having small design features and high circuit density. The invention is also applicable to the formation of any of various other types of semiconductor devices in which high circuit density is important, and hence, details have not been set forth in order to avoid obscuring the thrust of the invention.

In addition, no element, act or process used in the description of the invention should be construed as critical or essential to the invention unless explicitly described as such. Also, as used herein, the article “a” is intended to include one or more items. Where only one item is intended, the term “one” or similar language is used.

Only the preferred embodiments of the invention and a few examples of its versatility are shown and described in the present disclosure. It is to be understood that the invention is capable of use in various other combinations and environments and is capable of modifications within the scope of the inventive concept as expressed herein. 

What is claimed is: 1-20. (canceled)
 21. A method comprising: forming a plurality of memory cells on a substrate of a memory device, comprising: forming a multi-layer dielectric layer and a control gate electrode layer overlying the and substrate; and patterning the control gate electrode layer and the multi-layer dielectric layer; forming first spacers adjacent to a first memory cell of the plurality of memory cells, each of the first spacers being formed on one of opposite sides of the first memory cell; forming second spacers adjacent to a second memory cell of the plurality of memory cells, each of the second spacers being formed on one of opposite sides of the second memory cell, wherein first and second memory cells are adjacent to one another; forming an interlayer dielectric layer over the plurality of memory cells, the first spacers, and the second spacers, the interlayer dielectric layer substantially contacting the first spacers and the second spacers; forming a contact hole, through the interlayer dielectric layer to reach at least the substrate, between the first and second memory cells, a particular first spacer of the first spacers, and a particular second spacer of the second spacers, being adjacent to sidewalls of the contact hole; subsequent to forming the contact hole, forming a third spacer adjacent to the particular first spacer and a fourth spacer adjacent to the particular second spacer; and forming a contact in the contact hole.
 22. The method of claim 21, wherein the third and fourth spacers are formed in direct contact with the substrate and wherein a width of the third spacer and a width of the fourth spacer range from about 50 Å to about 400 Å.
 23. The method of claim 21, wherein a width of each of the first spacers ranges from about 50 Å to about 400 Å, and wherein a width of each of the second spacers ranges from about 50 Å to about 400 Å.
 24. The method of claim 21, wherein the first and second spacers are formed in direct contact with the substrate.
 25. The method of claim 21, wherein a top surface of each of the first spacers is substantially co-planar with the top surface of the control gate electrode layer of the first memory cell, and wherein a top surface of each of the second spacers is substantially co-planar with the top surface of the control gate electrode layer of the second memory cell.
 26. The method of claim 21, wherein the third spacer is formed to prevent charge leakage between the contact and the first memory cell, and wherein the fourth spacer is formed to prevent charge leakage between the contact and the second memory cell.
 27. The method of claim 21, wherein each of the first spacers, the second spacers, the third spacer, and the fourth spacer comprise a nitride layer.
 28. The method of claim 21, wherein the multi-layer dielectric layer includes a tunnel oxide layer, a charge trapping nitride layer, and a blocking oxide layer.
 29. The method of claim 21, wherein the control gate electrode layer includes at least one of: polycrystalline silicon, germanium, silicon-germanium, titanium, and tungsten.
 30. A method comprising: forming adjacent first and second memory cells on a substrate of a memory device, wherein each of the first and second memory cells includes a charge trapping layer formed between two dielectric layers and a gate electrode layer; forming first spacers adjacent to the first memory cell, each of the first spacers being formed on one of opposite sides of the first memory cell; forming second spacers adjacent to a second memory cell, each of the second spacers being formed on one of opposite sides of the second memory cell; forming a first interlayer dielectric layer over the first memory cell, the second memory cell, the first spacers, and the second spacers, the interlayer dielectric layer substantially encapsulating the first spacers, the second spacers, and the first and second memory cells; forming a contact hole, through the interlayer dielectric layer to at least reach the substrate, between the first memory cell and the second memory cell, one of the first spacers and one of the second spacers being adjacent to sidewalls of the contact hole; subsequent to forming the contact hole, forming a third spacer adjacent to the one of the first spacers and a fourth spacer adjacent to the one of the second spacers; and forming a contact adjacent and in contact with the third and fourth spacers.
 31. The method of claim 30, further comprising: forming at least one source/drain. region between the first and second memory cells in the substrate, wherein the contact is directly in contact with the at least one source/drain region.
 32. The method of claim 30, wherein the third and fourth spacers have a greater height than the first and second spacers.
 33. The method of claim 30, wherein the first interlayer dielectric layer comprises at least one of a hero-phsphosilicate glass (BPSG) material and a phosphosilicate glass (PSG) material.
 34. The method of claim 30, wherein a width of the contact hole ranges from about 0.1 micrometers (μm) to about 0.3 μm.
 35. The method of claim 30, wherein the first, second, third, and fourth spacers comprise a nitride layer.
 36. The method of claim 30, wherein the contact has a width ranges from about 400 Å to about 900 Å.
 37. The method of claim 31, wherein the contact forms a portion of a bit line coupling to the first and second memory cells.
 38. The method of claim 30, further comprising: planarizing the interlayer dielectric layer and the contact to forma planarized top surface; forming a first conductive interconnect line over the planarized top surface; forming a second interlayer dielectric layer over the conductive interconnect line; forming a via through the second interlayer dielectric layer; forming a second conductive interconnect line over the second interlayer dielectric layer.
 39. The method of claim 38, wherein the via connects the first and second conductive interconnect lines.
 40. The method of claim 30, wherein the third spacer is formed to prevent charge leakage between the contact and the first memory cell, and wherein the fourth spacer is formed to prevent charge leakage between the contact and the second memory cell. 